Start-Stop and Count Gate Generator

4.2.5

(Cont'd)

A. Time Base Generator (Cont'd)

as if coincidence had occurred even though no counts have been received within the decade

counters. To take care of this special condition, a bistable flip-flop Z9-5 has been included that

operates off of the carry signal from the last decade Z34 and the reset command. IC gate Z11-5

detects that the coincidence summing junction is in the high state and, therefore, enables Z11-13.

This enables the carry signal from Z34 through inverting gate Zll-9, to set the toggle flip-flop. The

delay introduced by the RC network in the gate line from the coincidence summing junction is to

assure that the reset pulse has cleared Z9-6 before the necessary clock pulse is present at Z9-5 to

set the flip-flop as required to indicate coincidence. In this situation, the output of Z9-8 serves as the

coincidence signal to end the count gate.

B. Start-Stop and Count Gate Generator

The first pulse leaving the signal gate Z14-11 and entering the count gate delay generator Z5-1 after

completion of reset is the internal start command that will initiate the count gate. NAND gates Z5-3,

Z5-6 and the associated components form a mono-stable multivibrator (one-shot) which introduces a

delay of approximately 500-750 nanoseconds. This delay balances the circuit delays caused by the

propagation time through the time base generator scalers and coincidence detecting system.

Depending upon the setting of the function switch, the delayed pulse train will pass through gates Z5-

12, & Z6-13 to set flip-flop Z8-12. The flip-flops Z8-12 and Z9-1 are essentially a two-stage counter

that work to control the count gate and display logic. The truth table and description shown in the

accompanying table (Fig.4-2) will help to illustrate the functions of this two-stage counter. Once the

first stage Z8-12 has been set, then the Count Gate Z4-8 enables the Time Base Gate Z14-1 and

Totalizer Gate Z2-5. This condition will exist until coincidence has occurred or the counter is reset by

external methods. Once Z8-12 has been set by the initial delayed trigger pulse, further pulses from

the delay generator Z5-6 are prevented from triggering Z8 by the low output of Z5-8. However, once

coincidence has occurred, the NAND gate Z7 is enabled by the presence of the coincidence signal at

pin 4. This then allows the next delayed pulse to trigger Z8. Since Z7-6 through Z5-8 has enabled

4-18