Time Base Generator-continued

4.2.5

(Cont'd)

A. Time Base Generator (Cont'd)

change will occur after coincidence is achieved in the Time Base Generator or when reset is

initiated.

The thumbswitch coincidence circuit operates in conjunction with the decade scalers Z19 through

Z34. NOR gates Z29 through Z35 are used to compare the scaler count to the thumbswitch setting.

These NOR gates drive the coincidence summing and inverting NAND gates Z24 through Z36 which

are connected in a "wired OR" configuration. The line common to the output of these NAND gates is

low (Logic "0") once a number has been set into any of the thumbswitches, and when coincidence is

achieved, this level changes to the high level (Logic "1"). For this to occur, the output of each NOR

gate Z29 through Z35 must be at, or changed to, the low level.

The NOR gate used in this counter differs from the NAND gate in that its output is low when either or

both inputs are high. Note that the thumbswitch input to each NOR gate is connected to +5 volts

through a resistor. Therefore, unless a thumbswitch number has been selected, these inputs remain

high and essentially lock out that gate from the active coincidence process. When a number is set

into the BCD thumbswitches, the appropriate 1, 2, 4, 8 lines are sent low (grounded) and the

corresponding NOR input from the scaler then becomes active in the coincidence process.

The Time base counting process always begins from a "cleared" or reset condition. All scalers in the

system start from the zero state, i.e., all output lines are low, and consequently, both inputs to the

NOR gates selected by the thumbswitches are initially low. The output of these NOR gates will

change from high to low only when the input line from the associated scaler changes to the high level

by virtue of the count accumulated in the scalers matching the number selected. The coincidence

condition, therefore, defined as a level change from low to high on "the common line" or summing

junction of all of the coincidence NAND gates (pin 4 of Z7) occurs when all of the conditions cited

above are satisfied.

A special condition of the coincidence detector occurs when the thumbswitches are set to .000000

(actual gate time of 10.00000 seconds). When this situation arises, the summing junction appears

4-17