Functional Block Diagrams

4.2.1

(Cont'd)

The IC's chosen for use in the Counters are the TTL family. These units provide fast response with high

immunity to noise. All IC's are mounted in the dual-in-line package for insertion in plug-in sockets. The

TTL logic levels for all IC's except the readout tube drivers is "O" equals +0.4 V maximum and "1" equals

+2.4 V minimum. The drawings contained in this section utilize standard nomenclature which is

explained below. All symbols are conventional with those contained in typical IC literature.

A circle on any lead leaving or entering an IC indicates that this point is low ("0") when the unit is

operational. That is, for a NAND gate, the output is low ("0") when all inputs are high (+, "1").

R-

Reset input.

oC -

Clock input. The outputs of Flip-Flops and Decade Counter elements change when a negative-

going excursion occurs at clock terminals so designated.

J-

When enabled, the next clock pulse will set the flip-flop.

K-

When enabled, the next clock pulse will reset the flip-flop.

JK -

When both J and K are enabled, then the flip-flop operates as a binary from the clock pulses.

Q-

Output with " "(low) when reset.

Q-

Complementary output or "1" (high, +) when reset.

4.2.2

Functional Block Diagrams

The many modes possible with the CF-604-6-8175SQ all use the same basic modules discussed in later

paragraphs. In order to facilitate understanding what part each of the modules play during a particular

mode of operation, the following simplified block diagrams trace the signal flow for each of the modes

selectable by the Mode Selector Switch.

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