Chassis Interconnection Diagram (Dwg. #0100-5097-03)

4.2.2

(Cont'd)

The PRESET COUNT mode of operation is identical to totalizing except that the addition of the

Thumbswitch scalers extends the scaling range and versatility.

4.2.3

Chassis Interconnection Diagram (Dwg. #0100-5097-03)

The Chassis Interconnection Diagram #0100-5097-03 shows the basic subassembly modules of the

counter, the associated controls and most of the interconnecting wiring that can be conveniently shown.

This diagram is most helpful in locating major functions and for general maintenance troubleshooting.

The numbers shown within the major sub-assemblies refer to schematics which are located in Section

4.4 of the manual.

The Input A signal enters the counter at J1 where it passes through the X1, X10 .and X100 attenuator

prior to reaching the Input Amplifier. For the FLOW input, this attenuator is bypassed via switch, S3.

Concentric to the Input Multiplier (attenuator) control is the vernier gain adjust R106. This control effects

the signal degeneration in the first stage of the Input Amplifier. The Input Amplifier conditions the signal

to a level suitable for operating the IC circuitry of the logic unit. The signal leaves the Input Amplifier at

Pin E of J11 and enters the logic board at Pin F of J12.

The Logic unit consists of numerous control gates. These various gates select the proper signal for

feeding to the Totalizer and the decade scalers and these gates are the Totalizer Count Gate, Time Base

Count Gate and Signal Gates. The duration of the Totalizer and Time Base Count Gates is determined

by the settings of the Thumbswitches S11 and the Multiplier Switch S9. Also within the Logic unit is

found all control circuitry required to generate display time, reset, start-stop logic and Thumbswitch

coincidence detection. This unit is the most complex portion of the Counter and a more detailed

discussion is contained in paragraph 4.2.4. The Chassis Interconnection Diagram shows the associated

controls that function with the Logic unit to determine the proper operating conditions. Critical signal flow

lines are also shown on this diagram and it will be noted that the gated input signal leaves the Logic unit

on Pin 5 of J12 and enters the totalizer on Pin 4 of J10. The reset command generated by the Logic unit

enters the totalizer on Pin E of J10. All signals contained in the CONTROL connector J5 at the rear of

the unit are indicated on the Chassis Interconnection Diagram and their appropriate connections to the

Logic unit are shown.

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