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4.2.5
(Cont'd)
B. Start-Stop and Count Gate Generator (Cont'd)
the K input to pin 9, this triggering action then sets Z9 and turns off the count gate. Z9 having been
set enables the operation of the display time circuit and automatic reset.
C. DISPLAY and RESET
The display time generator consists of transistors Q4 and Q5. Q5 is a unijunction oscillator which is
normally clamped by Q4 preventing oscillations. Once the output of Z9-13 switches low by virtue of
the completion of the counting cycle, then Q4 is cut off and Q5 is free to oscillate for one cycle only.
The duration of the cycle is determined by the setting of the DISPLAY TIME control. The DISPLAY
TIME control determines the rate at which C23 in the oscillator circuit can charge. When Q5 reaches
its trigger point, it conducts, and a potential is supplied to Z7-1 which sets Z8 for the second time. As
this occurs, NAND gate Z10-2 initiates the generation of the reset process via gate Z7-9. Gates Z7-8
and Z10-11 and their associated RC networks form a one-shot whose pulse duration is approximately
60 microseconds. Several NAND gates (Z10) are used to provide proper polarity reset signals for
the various functional units within the counter. The reset signal returns Z8 and Z9 to the initial
quiescent state where they remain until another start pulse arrives at the input to Z8-12. A reset
signal from Z10-8 also clears the decade scalers, and a signal from Z7-8 clears the Totalizer section.
D. Totalizer Overflow
Also contained on this board is the overflow (O/F) flip-flop, Z37-1 and -4. This flip-flop will set
whenever a negative pulse (carry) occurs at J13-Z. It is reset by Z10-6 in the normal reset action.
The output of the flip-flop is returned to the totalizer board and applied to a storage latch.
4.2.6
Totalizer (Sch.40104-5033-99)
The Totalizer unit consists of (decade counters, display tube drivers, and memory storage IC's. One of
each is used for every decade of the display. Schematic #0104-5033-99 shows the entire Totalizer unit.
4-20

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